The present invention relates to computer graphics controllers for connection to frame buffers, more particularly to access requests made to such computer graphics controllers, and even more particularly to the queuing, within such computer graphics controllers, of frame buffer addresses that are received from a split-response bus.
In computer systems, it is known in the art to utilize a computer graphics controller to serve as an interface between a video frame buffer, such as a video random access memory (VRAM), and other system components, such as one or more central processing units (CPUs) and other video input resources. Typically, the video frame buffer is coupled to the other system components by means of a system bus which conveys both address and pixel data information. The frame buffer stores pixel data that is intended to be retrieved and converted, as necessary, for display on an image display device, such as a cathode ray tube (CRT). The hardware which retrieves the pixel data from the frame buffer for conversion and presentation to the image display device is not usually coupled to the system bus, but instead has its own port for accessing the frame buffer.
The amount of time necessary for the frame buffer to access a location (either for reading or storing a pixel) is typically much slower than the operating speed of the system components requesting such accesses. To accommodate this mismatch in component operating speeds, it is possible to require that each frame buffer access request be held off (i.e., made to wait) until the frame buffer is finished with a present task and is ready to begin the next. However, if the system components that are making the access requests are themselves held off until such requests are serviced by the frame buffer, then the system bus will be tied up, thereby making it impossible for other system resources to perform even non-video related tasks. It is apparent that this situation will detrimentally affect system performance.
The problem is further compounded by the type of system bus that is utilized. Several bus characteristics may vary from system to system. For example, a device connected to the bus may be a master, a slave, or both. A master uses the system bus to issue requests for service to different slaves. A slave uses the system bus to respond to requests for service from different masters. A device may at one time issue a request for service and at another time respond to a request for service, thereby functioning as both a master and a slave.
Until recently, most small computer systems had only a single bus master that, with relatively few exceptions, enjoyed unrestricted access to the system bus. More recently, however, some personal computer systems have adopted a strategy, previously employed in minicomputers and mainframe computers, in which multiple bus masters are permitted to compete for access to the system bus through an arbitration process. In a typical personal computer (PC), for example, arbitrating devices may include a system microprocessor, processor-board DMA channels and expansion-slot bus master devices. It can be seen that, in such a system, the hoarding of bus resources by one bus master can significantly impact the performance of other potential bus masters.
Another characteristic of buses that affects system performance relates to the fact that a typical computer system bus is conceptually divided into an address bus, a data bus and a control bus. A bus transaction is a complete exchange between two bus devices, and typically comprises both an address phase, during which address information is presented on the address bus, and a data phase during which data information is presented on the data bus. The data phase of a bus transaction may follow the address phase of the same transaction in ordered succession, without any other data phase of any other bus transaction intervening. In such a case, the system bus is said to be "tightly ordered." Small computer systems are, as a general rule, tightly ordered.
By contrast, in some minicomputer and mainframe computers, and more recently in some small computer architectures, buses are "loosely ordered" such that, between the address phase of a bus transaction and the corresponding data phase, other data phases of other bus transactions may occur. The ability of the bus to allow the address bus and data bus to have different masters at the same time is called "split-bus transaction capability". The PowerPC.TM. computer architecture, co-developed by Apple Computer, utilizes a loosely ordered system bus that provides split-bus transaction capability.
PowerPC.TM. machines currently sold by Apple are based largely on the Motorola MPC601 RISC microprocessor. The MPC601 permits separate address bus tenures and data bus tenures, where tenure is defined as the period of bus mastership. In other words, rather than considering the system bus as an indivisible resource and arbitrating for access to the entire bus, the address and data buses are considered as separate resources, and arbitration for access to these two buses may be performed independently. A transaction, or complete exchange between two bus devices, is minimally comprised of an address tenure; one or more data tenures may also be involved in the exchange. The address and data tenures of each access request must be arbitrated separately from one another. However, the request for a data bus tenure is not made explicitly, but is instead implied by the occurrence of a corresponding address bus request/transaction. More information about the particulars of the system bus in the MPC601 RISC microprocessor may be found in the PowerPC 601 RISC Microprocessor User's Manual, published by Motorola in 1993, which is incorporated herein by reference. Another loosely coupled system bus is described in U.S. patent application Ser. No. 08/432,620, which was filed by James Kelly et al. on May 2, 1995, and entitled BUS TRANSACTION REORDERING USING SIDE-BAND INFORMATION SIGNALS, and which is incorporated herein by reference.
Returning to the discussion of the effect that frame buffer access time has on system bus delays, it is apparent that the presence of split-bus transaction capability adds a level of complexity that must be accounted for in any queuing mechanism whose purpose is to serve as a buffer between the presentation of a frame buffer access request and the servicing of that request. An instance of this added complexity may be seen by considering a frame buffer write request. In such a case, the queuing mechanism must be able to queue up both the address and the data. However, as explained above, not only do these not appear during the same bus tenure, but there may be intervening data bus tenures that are unrelated to the address. Thus, the queuing mechanism must be able to associate arriving data with the corresponding address. In addition, the queuing mechanism must be able to handle the appearance of addresses that, because they are associated with frame buffer read requests, should be presented to the frame buffer as soon as the frame buffer is free; there is no associated data to wait for.
Therefore, it is desirable to provide a queuing mechanism for a graphics controller, which queuing mechanism is capable of operating efficiently in a split-bus transaction environment. It is further desired to provide a queuing mechanism that will not, itself, be the cause of unnecessary delays in presenting access requests to the frame buffer at the moment that the frame buffer becomes free to handle a new request.